commit 48b7b9bd0e6ee241ec5f6317c2ce60eb1d30607d
author Igor Sysoev <igor@sysoev.ru> Tue Jan 29 07:06:18 2008 +0000
committer Igor Sysoev <igor@sysoev.ru> Tue Jan 29 07:06:18 2008 +0000
tree 70db50c4ed789cbd7d508822e1810a7e1a6a7fee
parent 442d1e63f267c5cb4ef9ed6f2b11158af33da68e

detect L2 cache line size for Intel Core

src/core/ngx_cpuinfo.c

diff --git a/src/core/ngx_cpuinfo.c b/src/core/ngx_cpuinfo.c
index 587f978..68eb094 100644
--- a/src/core/ngx_cpuinfo.c
+++ b/src/core/ngx_cpuinfo.c
@@ -96,9 +96,18 @@
 
         /* Pentium */
         case 5:
+            ngx_cacheline_size = 32;
+            break;
+
         /* Pentium Pro, II, III */
         case 6:
             ngx_cacheline_size = 32;
+
+            if ((cpu[0] & 0xf0) >= 0xd0) {
+                /* Intel Core */
+                ngx_cacheline_size = 64;
+            }
+
             break;
 
         /*